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74AC74 * 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
November 1988 Revised November 1999
74AC74 * 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
The AC/ACT74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to SD (Set) sets Q to HIGH level LOW input to CD (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH
Features
s ICC reduced by 50% s Output source/sink 24 mA s ACT74 has TTL-compatible inputs
Ordering Code:
Order Number 74AC74SC 74AC74SJ 74AC74MTC 74AC74PC 74ACT74SC 74ACT74SJ 74ACT74MTC 74ACT74PC Package Number M14A M14D MTC14 N14A M14A M14D MTC14 N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names D1 , D2 CP1, CP2 CD1, CD2 SD1, SD2 Q1, Q1, Q2, Q2 Description Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs
FACT is a trademark of Fairchild Semiconductor Corporation.
(c) 1999 Fairchild Semiconductor Corporation
DS009920
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74AC74 * 74ACT74
Logic Symbols
IEEE/IEC
Truth Table
(Each Half) Inputs SD L H L H H H CD H L L H H H CP X X D X X X H L X Outputs Q H L H H L Q0 Q L H H L H Q0

L
X
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial LOW-to-HIGH Clock Transition Q0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
=
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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74AC74 * 74ACT74
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Input Diode Current (IIK) VI = -0.5V VI = VCC + 0.5V DC Input Voltage (VI) DC Output Diode Current (IOK) VO = -0.5V VO = VCC + 0.5V DC Output Voltage (VO) DC Output Source or Sink Current (IO) DC VCC or Ground Current per Output Pin (ICC or IGND) Storage Temperature (TSTG) Junction Temperature (TJ) PDIP 140C 50 mA -65C to +150C 50 mA -20 mA +20 mA -0.5V to VCC + 0.5V -20 mA +20 mA -0.5V to VCC + 0.5V -0.5V to +7.0V
Recommended Operating Conditions
Supply Voltage (VCC) AC ACT Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate (V/t) AC Devices VIN from 30% to 70% of VCC VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate (V/t) ACT Devices VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V 125 mV/ns
Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications.
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC -40C to +85C
125 mV/ns
DC Electrical Characteristics for AC
Symbol VIH Parameter Minimum HIGH Level Input Voltage VIL Maximum LOW Level Input Voltage VOH Minimum HIGH Level Output Voltage VCC (V) 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 VOL Maximum LOW Level Output Voltage 3.0 4.5 5.5 3.0 4.5 5.5 IIN (Note 4) IOLD IOHD ICC (Note 4) Maximum InputLeakage Current Minimum Dynamic Output Current (Note 3) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 2.0 0.002 0.001 0.001 TA = +25C Typ 1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.1 0.1 0.1 0.36 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 VIN = VIL or VIH 2.46 3.76 4.76 0.1 0.1 0.1 VIN = VIL or VIH 0.44 0.44 0.44 1.0 75 -75 20.0 A mA mA A V IOL = 12 mA IOL = 24 mA IOL = 24 mA (Note 2) VI = VCC, GND VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND V IOUT = 50 A V IOH = -12 mA IOH = -24 m IOH = -24 m (Note 2) V IOUT = -50 A V VOUT = 0.1V or VCC - 0.1V V Units Conditions VOUT = 0.1V or VCC - 0.1V
Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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74AC74 * 74ACT74
DC Electrical Characteristics for ACT
Symbol VIH VIL VOH Parameter Minimum HIGH Level Input Voltage Maximum LOW Level Output Voltage Minimum HIGH Level Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Level Output Voltage 4.5 5.5 4.5 5.5 IIN ICCT IOLD IOHD ICC Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current (Note 6) Maximum Quiescent Supply Current 5.5 5.5 5.5 5.5 5.5 2.0 0.6 0.001 0.001 TA = +25C Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 0.1 TA = -40C to +85C Guaranteed Limits 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 1.0 1.5 75 -75 20.0 A mA mA mA A V Units V V V Conditions VOUT = 0.1V or VCC - 0.1V VOUT = 0.1V or VCC - 0.1V IOUT = -50 A VIN = VIL or VIH V IOH = -24 mA IOH = -24 mA (Note 5) IOUT = 50 A VIN = VIL or VIH V IOL = 24 mA IOL = 24 mA (Note 5) VI = VCC, GND VI = VCC - 2.1V VOLD = 1.65V Max VOHD = 3.85V Min VIN = VCC or GND
Note 5: All outputs loaded; thresholds on input associated with output under test. Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC Symbol Parameter (V) (Note 7) fMAX Maximum Clock Frequency tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn
Note 7: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 100 140 3.5 2.5 4.0 3.0 4.5 3.5 3.5 2.5 Typ 125 160 8.0 6.0 10.5 8.0 8.0 6.0 8.0 6.0 12.0 9.0 12.0 9.5 13.5 10.0 14.0 10.0 Max
TA = -40C to +85C CL = 50 pF Min 95 125 2.5 2.0 3.5 2.5 4.0 3.0 3.5 2.5 13.0 10.0 13.5 10.5 16.0 10.5 14.5 10.5 Max MHz Units
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
ns
ns
ns
ns
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74AC74 * 74ACT74
AC Operating Requirements for AC
VCC Symbol Parameter (V) (Note 8) tS Set-up Time, HIGH or LOW Dn to CPn tH Hold Time, HIGH or LOW Dn to CPn tW CPn or CDn or SDn Pulse Width trec Recovery Time CDn or SDn to CP
Note 8: Voltage Range 3.3 is 3.3V 0.3V Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 1.5 1.0 -2.0 -1.5 3.0 2.5 -2.5 -2.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 4.0 3.0 0.5 0.5 5.5 4.5 0 0 4.5 3.0 0.5 0.5 7.0 5.0 0 0 ns Units
3.3 5.0 3.3 5.0 3.3 5.0 3.3 5.0
ns
ns
ns
AC Electrical Characteristics for ACT
VCC Symbol Parameter (V) (Note 9) fMAX Maximum Clock Frequency tPLH Propagation Delay CDn or SDn to Qn or Qn tPHL Propagation Delay CDn or SDn to Qn or Qn tPLH Propagation Delay CPn to Qn or Qn tPHL Propagation Delay CPn to Qn or Qn
Note 9: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Min 145 Typ 210 Max
TA = -40C to +85C CL = 50 pF Min 125 Max MHz Units
5.0
5.0
3.0
5.5
9.5
2.5
10.5
ns
5.0
3.0
6.0
10.0
3.0
11.5
ns
5.0
4.0
7.5
11.0
4.0
13.0.
ns
5.0
3.5
6.0
10.0
3.0
11.5
ns
AC Operating Requirements for ACT
VCC Symbol Parameter (V) (Note 10) tS tH tW trec Set-up Time, HIGH or LOW Dn to CPn Hold Time, HIGH or LOW Dn to CPn CPn or CDn or SDn Pulse Width Recovery Time CDn or SDn to CP
Note 10: Voltage Range 5.0 is 5.0V 0.5V
TA = +25C CL = 50 pF Typ 1.0 -0.5 3.0 1.0
TA = -40C to +85C CL = 50 pF Guaranteed Minimum 3.5 1.0 ns ns Units
5.0 5.0
5.0
3.0 -2.5
5.0
6.0
ns
5.0
0
0
ns
Capacitance
Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 35.0 Units pF pF VCC = OPEN VCC = 5.0V Conditions
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74AC74 * 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150" Narrow Body Package Number M14A
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74AC74 * 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D
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74AC74 * 74ACT74
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14
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74AC74 * 74ACT74 Dual D-Type Positive Edge-Triggered Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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